Ming-Hong Lin

Master Student | Digital IC Design & AI Accelerators

Specializing in Low-Cost, High-Performance AI Accelerator Architecture Design

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About Me

Ming-Hong Lin

I am a master student at the National Taiwan University of Science and Technology, pursuing a Master's degree in Electrical Engineering with a focus on Integrated Circuits and Systems.

My research centers on developing innovative, low-cost AI accelerator architectures that achieve superior performance while maintaining high accuracy. I am passionate about pushing the boundaries of digital IC design, particularly in the areas of AI hardware acceleration and low-power design.

Research Interests

  • AI Accelerator Design
  • Low-Cost IC Design
  • Low-Power IC Design
  • Error Correction Codes (LDPC)

Education

Master of Science in Electrical Engineering

Feb. 2026 - Present

National Taiwan University of Science and Technology

Integrated Circuits and Systems

Taipei, Taiwan

Bachelor of Science in Electrical Engineering

Sept. 2022 - Dec. 2025

National Taiwan University of Science and Technology

Integrated Circuits and Systems

GPA: 4.03 / 4.30
Rank: 28 / 158 (Top 18%)
Selected Coursework:
  • Digital System Design (A+)
  • Digital System Design Practicum (A+)
  • Introduction to VLSI Designs (A+)
  • Computer Organization (A+)
  • FPGA System Design and Practicum (A+)

Publications

Weight-Aware and Reduced-Precision Architecture Designs for Low-Cost AI Accelerators

Shyue-Kung Lu, Yu-Xian Huang, Ming-Hong Lin, and Chia-Hung Hsiao

11th Taiwan and Japan Conference on Circuits and Systems (TJCAS 2025)

Low-Cost and High-Performance AI Accelerator Architecture Design Based on Weight Characteristics

Ming-Hong Lin, Chia-Hung Hsiao, and Shyue-Kung Lu

4th International Practical Applications Seminar on Electrical Engineering and Computer Science

Projects

Low-Cost & High-Performance AI Accelerator

Feb. 2025 - Oct. 2025

Based on Google's TPU Architecture

Developed an innovative AI accelerator architecture that performs compression and compensation based on bit-level weight distribution characteristics. The design achieves significant improvements in hardware efficiency, power consumption, and computational performance.

AI Accelerator Architecture

Architecture Diagram

AI Accelerator Floorplan

Floorplan

Key Achievements:

  • Reduced systolic array hardware cost by 16.4%
  • Decreased on-chip memory access by 18.46%
  • Achieved 6.54 TOPS higher throughput
  • Improved accuracy by ~1% over INT8 quantization for MLP and LeNet
Verilog Python AI Accelerator TPU Low-Power Design
View on GitHub

Five-Stage Pipelined RISC-V CPU on FPGA

Implemented a complete five-stage pipelined RISC-V processor supporting RV32I and RV32M instruction sets. The design includes advanced features such as 2-way set-associative caches with AXI-to-BRAM interface, data forwarding, hazard detection, and dynamic branch prediction.

Key Features:

  • Full RV32I/RV32M instruction set support
  • 2-way set-associative cache with AXI interface
  • Data forwarding and hazard detection units
  • Dynamic branch prediction for improved performance
Verilog RISC-V FPGA Vivado CPU Design
View on GitHub

LDPC Encoder & Decoder on FPGA

Based on IEEE 802.11n Standard

Designed and implemented high-performance LDPC encoder and decoder IP cores compliant with the IEEE 802.11n wireless communication standard. The encoder utilizes the Richardson–Urbanke algorithm and achieves 250 MHz operating frequency.

Key Features:

  • 250 MHz LDPC Encoder using Richardson–Urbanke algorithm
  • Decoder supporting code rates 1/2 and 2/3
  • IEEE 802.11n compliant design
  • Optimized for FPGA implementation
Verilog LDPC FPGA IEEE 802.11n Error Correction

Skills

IC Design Skills

  • System Modeling & Algorithms
  • RTL Design
  • Logic Synthesis
  • APR (Automatic Place and Route)
  • FPGA System Design

Design Tools

  • ModelSim
  • Vivado
  • Design Compiler
  • IC Compiler

Programming Languages

  • Verilog
  • SystemVerilog (Basic)
  • Python
  • C/C++ (Basic)

Languages

  • Mandarin (Native)
  • English (Professional)

Work Experience

FPGA Digital IC Design Intern

Ranictek

Sept. 2025 - Present

Developing advanced LDPC (Low-Density Parity-Check) algorithms and designing high-performance encoder/decoder IP cores for error correction applications.

Key Achievements:
  • Designed 250 MHz LDPC Encoder using the Richardson–Urbanke algorithm
  • Developed LDPC Decoder supporting code rates 1/2 and 2/3
  • Implemented IP cores compliant with IEEE 802.11n standard
  • Optimized design for FPGA deployment and performance

Get In Touch

I'm always open to discussing new opportunities, collaborations, or research ideas. Feel free to reach out!

Email

harry2963753@gmail.com

Location

Taipei, Taiwan

LinkedIn

linkedin.com/in/-marco-lin

GitHub

github.com/akira2963753
Download My CV